Power Optimization of Interconnection Networks for Transport Triggered Architecture

Transport triggered architecture (TTA) has been shown to provide an efficient way to design application specific instruction set processors. However, the interconnection network of TTA is based on simple-bus, which consumes much extra power for specific data transport. In this paper, we employ segmented-bus to solve this problem. How to partition the buses lies on the placement of macro blocks, and the manual creation of an optimal placement would be a labor-intensive process, leading to high design costs. Instead, we propose automatic approach to place the macro blocks specialized to given applications. For several real life cryptographic applications, a factor of 1.14 in bus power reduction can be achieved while maintaining the same performance.